One of the challenges facing processor designers is the handling of an ever-increasing number of communications, both internal and external to the processor. Generally this is done by providing some kind of interrupt handling capability for the processor for reacting to certain types of activity. Increasingly, more sophisticated interface logic is used to deal with, for example, multiple external devices per port.
Conventionally, external interfacing is achieved either using interrupts or by polling. When interrupts are used, an external peripheral device sends a signal to inform the processor either that it has data ready to input to the processor or that it requires data from the processor. However, using interrupts, the current program state must be saved before the interrupt can be acted upon. When polling is used, the processor continually checks the state of the device to determine whether or not it is ready to supply or accept data. This introduces a delayed reaction time. Polling is also slow because of the continual queries and responses.
One improved approach to this which is discussed in our earlier U.S. application Ser. No. 11/717,623, our ref. 314563.US, entitled “Processor Register Architecture”, is to use a multi-threaded processor with threads dedicated to specific activities such as input/output events.
Existing multi-thread processors lack an efficient mechanism for communicating thread related activities. Communications between threads on the same processor are sometimes supported via shared registers or via memory. However, use of shared registers complicates the processor architecture, and requires more operand access in instructions. Use of shared memory increases power and delay, and requires execution of more instructions.
Communications between threads on different processors is sometimes supported by shared registers, or alternatively communication links are used. Use of shared memory complicates the system architecture and consumes power, and also does not provide efficient communication for reacting to stimuli. Communications links usually impose significant software overheads as they are designed to transfer large blocks of data typically using Direct Memory Access (DMA).